Systems and Means of Informatics

2026, Volume 36, Issue 2, pp 3-17

TEMPLATE-BASED SELF-TIMED COUNTER DESIGN

Yu. A. Stepchenkov
Yu. G. Diachenko
D. V. Khilko
G. A. Orlov
G. S. Appolonov
D. Yu. Diachenko

Abstract

The article explores the self-timed (ST) binary counter automated design based on the initial Verilog description of a synchronous prototype. Counters are among the most popular digital units used in robotic systems. Typical synchronous circuit synthesizers construct counters using a storage register and a combinational environment that calculates a new counter state based on its current state and the signal values that determine the counter's properties. However, in most cases, this approach to ST counter synthesis results in excessive hardware redundancy and degraded counter performance. However, circuit design solutions for sequential ST counters are available that ensure minimal hardware costs and acceptable performance. The design features of ST counters with various options for asynchronous and self-timed setup as well as operation-enable features are examined. A method for the ST counter formalized construction based on the use of ready-made hardware blocks - templates - that implement the specific features of their behavior is proposed. The ST counter's Verilog description is assembled from hardware modules corresponding to the specified synthesized counter's options. The proposed template method enables the synthesis of binary ST counters of various types (up, down, and reversible), automates the creation of a cell library for ST circuit synthesis, and guarantees the self-timing of the resulting hardware counter implementations.

[+] References (24)

Afrin, S., S. Roksana, and R. Akram. 2025. Al-enhanced robotic process automation: A review of intelligent automation innovations. IEEE Access 13:173-197. doi: 10.1109/ACCESS.2024.3513279. EDN: DRFTAS.
Kozov, V., A. Ivanov, and G. Ivanova. 2025. A eneralized review of recent robotics research (2020-2024). 24th Symposium (International) INFOTEH-JAHORINA Proceedings. IEEE. Art. 10959238. 5 p. doi: 10.1109/INFOTEH64129.2025.10959238.
Harris, D., and S. L. Harris. 2013. Digital design and computer architecture. Amsterdam, The Netherlands: Elsevier. 690 p.
Hennessy, J.L., and D.A. Patterson. 2019. Computer architecture: A quantitative approach. 6th ed. San Mateo, CA: Morgan Kaufmann. 936 p.
Anirudh, S., and T. K. Ramesh. 2022. An enhanced clock tree synthesis methodology for optimizing power in physical design. 3rd Conference (International) on VLSI Systems, Architecture, Technology and Applications Proceedings. IEEE. Art. 10046629. 9 p. doi: 10.1109/VLSISATA54927.2022.10046629.
Martirosov, V. E., and G. A. Alekseev. 2023. Metody vysokoskorostnoy sinkhronizatsii v sistemakh fazovoy avtopodstroyki chastoty [Methods of high-speed synchronization in PLL systems]. Radiotekhnika [Radioengineering] 87(3):83-91. doi: 10.18127/ j00338486-202303-08. EDN: JCCXZL.
Wiesner, A., and T. Kovacshazy. 2025. An innovative method to enhance PLL resolution in synchronized embedded systems. IEEE T. Instrum. Meas. 74:3002312. 12 p. doi: 10.1109/TIM.2025.3584124.
Sparso, J., and S. Furber. 2001. Principles of asynchronous circuit design: A systems perspective. New York, NY: Springer. 337 p. doi: 10.1007/978-1-4757-3385-3.
Varshavsky, V.I., M.A. Kishinevsky, V.B. Marakhovsky, and V.A. Peschansky. 1990. Self-timed control of concurrent processes. Kluver Academic Publs. 245 p.
Fant, K. M. 2005. Logically determined design: Clockless system design with NULL convention logic. New York, NY: John Wiley. 292 p. doi: 10.1002/0471702897.
Kushnerov, A., M. Medina, and A. Yakovlev. 2021. Towards hazard-free multiplexer based implementation of self-timed circuits. 27th Symposium (International) on Asynchronous Circuits and Systems Proceedings. IEEE. 17-24. doi: 10.1109/ASYNC48570.2021.00011.
Zakharov, V.N., Yu. A. Stepchenkov, Yu. G. Diachenko, N. V. Morozov, L. P. Plekhanov, and D.Yu. Stepchenkov. 2025. Svoystva i optimizatsiya samosinkhronnykh skhem [Properties and optimization of self-timed circuits]. Sistemy i Sred- stva Informatiki - Systems and Means of Informatics 35(1): 149-169. doi: 10.14357/08696527250108. EDN: QPTSAO.
Plekhanov, L. P., and Yu. A. Stepchenkov. 2006. Eksperimental'naya proverka nekotorykh svoystv strogo samosinkhronnykh skhem [Experimental verification of some properties of strictly self-timed circuits]. Sistemy i Sredstva Informatiki - Systems and Means of Informatics 16:476-485. EDN: KZUWOX.
Sokolov, I. A., Yu. A. Stepchenkov, Yu. V. Rogdestvenski, and Yu. G. Diachenko. 2022. Approximate evaluation of the efficiency of synchronous and self-timed methodologies in problems of designing failure-tolerant computing and control systems. Automat. Rem. Contr. 83(2):264-272. doi: 10.1134/S0005117922020084. EDN: CDSNSD.
Zhou, R., K.-S. Chong, B.-H. Gwee, J. S. Chang, and W.-G. Ho. 2014. Synthesis of asynchronous QDI circuits using synchronous coding specifications. Symposium (International) on Circuits and Systems Proceedings. IEEE. 153-156. doi: 10.1109/ISCAS.2014.6865088.
Oliveira, D. L., G. C. Duarte, G. C. Batista, and N. N. M. Cardoso. 2020. Converting synchronous digital systems to asynchronous systems using local-clock. 27th Conference (International) on Electronics, Electrical Engineering and Computing Proceedings. IEEE. Art. 9220269. 4 p. doi: 10.1109/INTERC0N50315.2020.9220269.
Plekhanov, L. P. 2013. Osnovy samosinkhronnykh elektronnykh skhem [Basics of self-timed electronic circuits]. Moscow: BINOM; Laboratoriya znaniy. 208 p. EDN: SUMKIV.
Oliveira, D.L., N. N. M. Cardoso, and G. C. Batista. 2021. A new method for synthesis of self-timed combinational circuits with strong indication. 5th Ecuador Technical Chapters Meeting Proceedings. IEEE. Art. 9590822. 6 p. doi: 10.1109/ ETCM53643.2021.9590822.
Sudeng, S., and A. Thongtak. 2008. Synthesis of complicated asynchronous control circuits using template based technique. World Congress on Engineering Proceedings. London, U.K.: NewswoodLtd. I:462-467.
Stepchenkov, Y., Y. Diachenko, and D. Khilko. 2025. Mapping self-timed sequential circuits on the basis of the original synchronous counterpart description. Conference (International) on Industrial Engineering, Applications and Manufacturing Proceedings. IEEE. 837-842. doi: 10.1109/ICIEAM65163.2025.11028582.
Plekhanov, L.P., Yu.G. Diachenko, D.V. Khilko, and G. A. Orlov. 2025. Optimizatsiya sinteza posledovatel'nostnykh samosinkhronnykh skhem po sinkhronnomu opisaniyu [Template method in synthesis of self-timed digital circuits]. Sistemy i Sredstva Informatiki - Systems and Means of Informatics 35(4):4-19. doi: 10.14357/ 08696527250401. EDN: THWOVK.
Yosys open synthesis suite. Available at: https://yosyshq.net/yosys (accessed May 6, 2026).
Stepchenkov, Yu. A., Yu.G. Diachenko, N. V. Morozov, D.Yu. Stepchenkov, and D. Yu. Diachenko. 2024. Formalizatsiya sinteza samosinkhronnykh schetchikov [Self-timed counter synthesis formalization]. Sistemy i Sredstva Informatiki - Systems and Means of Informatics 34(2):66-82. doi: 10.14357/08696527240205. EDN: KDIEOJ.
Stepchenkov, Yu. A., D. V. Khilko, Yu. G. Diachenko, N. V. Morozov, D.Yu. Stepchenkov, and G. A. Orlov. 2024. Metodika desinkhronizatsii pri sinteze samosinkhronnykh skhem [Desynchronization methodology at self-timed circuit synthesis]. Sistemy i Sredstva Informatiki - Systems and Means of Informatics 34(1):33-43. doi: 10.14357/08696527240103. EDN: XGZCWU.

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