Systems and Means of Informatics

2026, Volume 36, Issue 1, pp 3-21

SELF-TIMED FIFO IMPLEMENTATION

  • Yu. G. Diachenko
  • N. V. Morozov
  • D. Yu. Stepchenkov
  • D. Yu. Diachenko

Abstract

The article focuses on the interface development for self-timed (ST) circuits interacting with both synchronous and ST environments, specifically on a FIFO (First Input First Output) data reception buffer register. The request-acknowledge nature of ST circuits interacting with their environment, the absence of a global clock signal, and their independence from the actual delays of logic cells leads to unspecified input data processing times. The environmental conditions and the data itself determine the time it takes for appearing valid result at the ST circuit's output. To improve the performance of a computing system incorporating both synchronous and ST circuits, it is advisable to use a FIFO for exchanging data and the results of their processing. A FIFO allows one to mask the discrepancy between the frequency of input data receipt and the time it takes to process it in a ST circuit. The article examines the design features of ST FIFO, proposes cases for their implementation, analyzes their consumer characteristics, and substantiates the conclusion that, based on the totality of consumer characteristics, the best choice is ST FIFO on hysteretic latches, which provides maximum performance with a slight deterioration in hardware complexity if the FIFO capacity exceeds four operands.

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