Systems and Means of Informatics
2025, Volume 35, Issue 2, pp 3-16
COMBINED ENCODING IN ELEMENTS OF FIELD-PROGRAMMABLE GATE ARRAYS
- S. F. Tyurin
- I. A. Vasenin
- Yu. A. Stepchenkov
- Yu. G. Diachenko
Abstract
The authors consider the variables' combined coding of a Lookup Table (LUT) logical element and a routing multiplexer that is an interconnect switch of the Field-Programmable Gate Array (FPGA). The proposed method of combining positional and unitary coding ensures the reduction of the logical function calculation delay under given hardware limitations or the reduction of the communication switch hardware costs under restrictions on the delay. The paper describes a model of such encoding and a method for synthesizing the corresponding element. It provides complexity estimates in terms of transistors and results of circuit and layout simulation. Simulation proves the proposed element's performance. The analysis shows the effectiveness of the adopted approach in terms of complexity, layout area, time delay, and power consumption.
The developed element with combined encoding can significantly reduce the time delay when calculating functions of a large variable number and the interconnect configuration memory volume.
[+] References (21)
- Stepchenkov, Yu. A., N. V. Morozov, Yu. G. Diachenko, D.V. Khilko, and D. Yu. Stepchenkov. 2020. Razvitie gibridnoy mnogoyadernoy rekurrentnoy arkhitektury na PLIS [Multicore hybrid recurrent architecture expansion on FPGA]. Sistemy i Sredstva Informatiki - Systems and Means of Informatics 30(4):95-101. doi: 10.14357/08696527200409. EDN: ALLSBO.
- Tyurin, S.F., S.I. Sovetov, Yu. A. Stepchenkov, and Yu. G. Diachenko. 2024. Novyy podkhod k realizatsii logicheskikh funktsiy v programmiruemykh logicheskikh integral'nykh skhemakh [A new approach to implementing logical functions in field- programmable gate arrays]. Sistemy i Sredstva Informatiki - Systems and Means of Informatics 34(4):3-15. doi: 10.14357/08696527240401. EDN: TCWBAG.
- Sokolov, I. A., S. F. Tyurin, Yu. A. Stepchenkov, Yu. G. Diachenko, M. S. Nikitin, and S. I. Sovetov. 2024. Novaya kontseptsiya PLIS s vyborom rezhima raboty i dvukh- rezhimnyy bazisnyy logicheskiy element [Novel FPGA clock concept and dual-mode basic logic gate]. Sistemy vysokoy dostupnosti [Highly Available Systems] 20(2):56-64. doi: 10.18127/j20729472-202402-04. EDN: YHCZJP.
- Strogonov, A., M. Krivchun, and P. Gorodkov. 2020. Obzor programmnykh sredstv s otkrytym iskhodnym kodom dlya issledovaniya sovremennykh arkhitektur PLIS XILINX [Overview of open source software tools for researching modern XILINX FPGA architectures]. Elektronika: Nauka, tekhnologiya, biznes [Electronics: Science, Technology, and Business] 1(192):100{107. doi: 10.22184/1992-4178. 2020.192.1.100.107. EDN: UPNZSW.
- Strogonov, A., and P. Gorodkov. 2020. Sovremennye tendentsii razvitiya PLIS: ot sistemnoy integratsii k iskusstvennomu intellektu [Current trends in FPGA development: From system integration to artificial intelligence]. Elektronika: Nauka, tekhnologiya, biznes [Electronics: Science, Technology, and Business] 4(195):46{56. doi: 10.22184/ 1992-4178.2020.195.4.46.56. EDN: QOABOZ.
- Strogonov, A. 2023. Proektirovanie konechnykh avtomatov v prilozhenii STATE- FLOW sistemy MATLAB/SIMULINK s posleduyushchey realizatsiey v bazise PLIS [Designing finite-state machine in MATLAB/SIMULINK system's stateflow tool with subsequent implementation at the FPGA basis]. Elektronika: Nauka, tekhnologiya, biznes [Electronics: Science, Technology, and Business] 3(224):134{147. doi: 10.22184/1992-4178.2023.224.3.134.146. EDN: BDJLBU.
- Strogonov, A., and P. Gorodkov. 2020. PLIS kompanii Guangdong Gowin Semiconductor Corporation [FPGA from Guangdong Gowin Semiconductor Corporation]. Komponenty i tekhnologii [Components and Technologies] 1(222):84{86. EDN: BIUCZX.
- Strogonov, A., and P. Gorodkov. 2022. Obzor PLIS kitayskikh proizvoditeley [Overview of FPGAs from Chinese manufacturers]. Elektronika: Nauka, tekhnologiya, biznes [Electronics: Science, Technology, and Business] 4(215):66{75. doi: 10.22184/ 1992-4178.2022.215.4.66.74. EDN: ZFMFUX.
- Arbuzov, I., A. Strogonov, and P. Gorodkov. 2019. Primer razrabotki proekta v bazise PLIS 5578TC024 [An example of project development based on FPGA 5578TS024]. Komponenty i tekhnologii [Components and Technologies] 7(216):66{69. EDN: GGJBLH.
- Mahendra, P., and S. R. Ramesh. 2022. FPGA implementation of high performance precise signed and unsigned multiplier using ternary 6-LUT architecture. Conference (International) on Inventive Computation Technologies Proceedings. IEEE. 202{207. doi: 10.1109/ICICT54344.2022.9850686.
- Pirogov, A. A., Yu. A. Pirogova, A. V. Bashkirov, M. Yu. Chepelev, and B. I. Zhilin. 2020. Metodika proektirovaniya preobrazovatelya koda Greya na PLIS [Design procedure of the Gray code converter on FPGA]. Vestnik Voronezhskogo instituta FSIN Rossii [Vestnik of Voronezh Institute of the Russian Federal Penitentiary Service] 3:9G4. EDN: QHAANU.
- Strogonov, A. V., and S. A. Tsybin. 2010. Programmiruemaya kommutatsiya PLIS: vzglyad iznutri [FPGA programmable switching: An inside look]. Komponenty i tekh- nologii [Components and Technologies] 11(112):56{62. EDN: NEIPHH.
- Tyurin, S.F., I. A. Vasenin, and S.I. Sovetov. 2023. Logicheskie elementy PLIS FPGA na osnove kombinirovannogo kodirovaniya peremennykh [FPGA gates using combined variables coding]. Vestnik Permskogo natsional'nogo issledovatel'skogo po- litekhnicheskogo universiteta. Elektrotekhnika, informatsionnye tekhnologii, sistemy upravleniya [PNRPU Bulletin. Electrical Engineering, Information Technology, Control Systems] 46:83G07. doi: 10.15593/2224-9397/2023.2.04. EDN: XOKIEK.
- Vasenin, I. A., S.I. Sovetov, N. E. Oputin, and S.F. Tyurin. 2023. Advanced logic gates for FPGAs. 24th Conference (International) of Young Professionals in Electron Devices and Materials Proceedings. IEEE. 110U15. doi: 10.1109/ EDM58354.2023.10225215.
- Zhang, J., K. Zhu, K. Shi, L. Wang, and H. Zhou. 2023. Efficient FPGA routing architecture exploration based on two-stage MUXes. 15th Conference (International) on ASIC Proceedings. IEEE. Art. 10395964. 4 p. doi: 10.1109/ASICON58565.2023. 10395964.
- Vikhorev, R. 2016. Universal logic cells to implement systems functions. NW Russia Young Researchers in Electrical and Electronic Engineering Conference Proceedings. IEEE. 373{375. doi: 10.1109/EIConRusNW.2016.7448197.
- Vikhorev, R. 2018. Improved FPGA logic elements and their simulation. Conference of Russian Young Researchers in Electrical and Electronic Engineering Proceedings. IEEE. 259{264. doi: 10.1109/EIConRus.2018.8317080.
- Tyurin, S. F., and R. V. Vikhorev. 2021. A decoder - look up tables for FPGAs. Int. J. Computing 20(3):365{373. doi: 10.47839/ijc.20.3.2282.
- Mead, C. A., and L. Conway. 1979. Introduction to VLSI systems. 2nd ed. Reading, MA: Addison-Wesley. 396 p.
- MicroWind ver.3.5. Available at: https://microwind.net/downloads (accessed March 31, 2025).
- Tyurin, S. F., I. A. Vasenin, Yu. A. Stepchenkov, Yu. G. Diachenko, and S. I. Sovetov. 02.08.2023. Programmiruemoe logicheskoe ustroystvo [Programmable logic device]. Patent RFNo.2811404. EDN: COOGKL.
[+] About this article
Title
COMBINED ENCODING IN ELEMENTS OF FIELD-PROGRAMMABLE GATE ARRAYS
Journal
Systems and Means of Informatics
Volume 35, Issue 2, pp 3-16
Cover Date
2025-05-20
DOI
10.14357/08696527250201
Print ISSN
0869-6527
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
FPGA's elements; LUT; routing multiplexer; unitary and positional encoding
Authors
S. F. Tyurin  ,  , I. A. Vasenin  , Yu. A. Stepchenkov  , and Yu. G. Diachenko
Author Affiliations
 Perm National Research Polytechnic University, 7 Prof. Pozdeev Str., Perm 614013, Russian Federation
 Perm State University, 15 Bukireva Str., Perm 614990, Russian Federation
 Federal Research Center "Computer Science and Control", Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
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