Systems and Means of Informatics
2023, Volume 33, Issue 1, pp 4-13
SELF-TIMED PIPELINE WITH VARIABLE STAGE NUMBER
- I. A. Sokolov
- Yu. A. Stepchenkov
- Yu. G. Diachenko
- N. V. Morozov
- D. Yu. Diachenko
Abstract
The article considers the self-timed circuit's performance improvement problem. As in synchronous circuits, an effective way to improve performance is to use a pipeline to implement multistage input data processing. The article analyzes possible options for dynamical reduction of the number of actively operating stages under certain conditions determined by the processed data value or an external signal. The estimates show that the efficiency of using an optionally variable number of pipeline stages depends on the number of bypassed stages and the probability of an event allowing this bypassing. In particular, replacing two successive pipeline stages with one parallel stage becomes expedient if it occurs in at least 63% of data processing operations and bypassing two or more stages reduces the average pipeline's latency if it occurs in at least 43% of operations.
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[+] About this article
Title
SELF-TIMED PIPELINE WITH VARIABLE STAGE NUMBER
Journal
Systems and Means of Informatics
Volume 33, Issue 1, pp 4-13
Cover Date
2023-05-11
DOI
10.14357/08696527230101
Print ISSN
0869-6527
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
self-timed circuit; pipeline; bypassing; multiplexing; latency; performance
Authors
I. A. Sokolov  , Yu. A. Stepchenkov , Yu. G. Diachenko , N. V. Morozov , and D. Yu. Diachenko
Author Affiliations
Federal Research Center "Computer Science and Control", Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
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