Systems and Means of Informatics
2022, Volume 32, Issue 4, pp 4-13
SELF-TIMED PIPELINE'S SOFT ERROR TOLERANCE ANALYSIS
- I. A. Sokolov
- Yu. A. Stepchenkov
- Yu. G. Diachenko
- N. V. Morozov
- D. Yu. Stepchenkov
- D. Yu. Diachenko
Abstract
Practical self-timed (ST) circuits are implemented as a pipeline, similar to synchronous circuits. Self-timed circuits have a number of advantages in comparison with synchronous counterparts but are redundant in hardware.
The article analyzes the tolerance of the ST pipeline to single soft errors, taking into account its hardware redundancy and assuming that each soft error affects only one circuit's logical cell. Due to their two-phase work discipline and the mandatory indication of the successful completion of the switching in each phase, the ST circuits can detect a soft error and suspend the operation of the circuit until it disappears. A failure-tolerant hysteretic latch as a part of the pipeline stage register bit ensures that the register is immune to any soft error in the pipeline stage's combinational part. The DICE-like implementation of this latch increases the ST register tolerance to internal soft errors by a factor of 2.7. In general, the ST pipeline is 2.5-6.8 times more immune to single soft errors than its synchronous counterpart.
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[+] About this article
Title
SELF-TIMED PIPELINE'S SOFT ERROR TOLERANCE ANALYSIS
Journal
Systems and Means of Informatics
Volume 32, Issue 4, pp 4-13
Cover Date
2022-30-11
DOI
10.14357/08696527220401
Print ISSN
0869-6527
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
self-timed circuits; pipeline; soft error; failure tolerance; indication; hysteretic trigger
Authors
I. A. Sokolov  , Yu. A. Stepchenkov , Yu. G. Diachenko , N. V. Morozov ,
D. Yu. Stepchenkov , and D. Yu. Diachenko
Author Affiliations
Federal Research Center "Computer Science and Control", Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
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