Systems and Means of Informatics
2022, Volume 32, Issue 3, pp 81-91
SELF-TIMED SHIFT REGISTER CASES
- Yu. A. Stepchenkov
- Yu. G. Diachenko
- Yu. V. Rogdestvenski
- N. V. Morozov
- D. Yu. Stepchenkov
- D. Yu. Diachenko
Abstract
The paper discusses the problems of designing and using self-timed (ST) shift registers. Self-timed circuits have their specifics: two-phase work discipline, redundant information coding, etc. Due to this, they have some advantages compared with synchronous counterparts: independence of behavior from cell delays, detection of any stuck faults, etc. The article considers implementation options for the ST shift register with various options, including setting to a spacer and presetting a fixed value in each bit of the shift register.
The proposed options have different functionality, complexity, and performance.
Shift registers based on RS-flip-flops have minimal hardware costs, while shift registers based on hysteretic triggers have better performance. The article analyzes shift register's characteristics and substantiates recommendations for their use as a serial-to-parallel port, parallel-to-serial port, or FIFO (First Input, First Output).
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[+] About this article
Title
SELF-TIMED SHIFT REGISTER CASES
Journal
Systems and Means of Informatics
Volume 32, Issue 3, pp 81-91
Cover Date
2022-06-11
DOI
10.14357/08696527220308
Print ISSN
0869-6527
Publisher
Institute of Informatics Problems, Russian Academy of Sciences
Additional Links
Key words
self-timed circuit; hysteretic trigger; RS-flip-flop; shift register; FIFO; serial-to-parallel port; hardware costs; performance
Authors
Yu. A. Stepchenkov  , Yu. G. Diachenko , Yu. V. Rogdestvenski , N. V. Morozov , D. Yu. Stepchenkov , and D. Yu. Diachenko
Author Affiliations
Federal Research Center "Computer Science and Control", Russian Academy of Sciences, 44-2 Vavilov Str., Moscow 119333, Russian Federation
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