Systems and Means of Informatics

2014, Volume 24, Issue 2, pp 55-66


  • V. S. Petrukhin
  • D. Y. Stepchenkov
  • N. V. Morozov
  • Y. A. Stepchenkov


A procedure of selecting and developing a software and hardware suite is studied which is intended for designing and debugging a nontraditional digital signal processor based on the recurrently-dynamic dataflow architecture | the recurrent signal processor (RSP). The experimental character of the developed RSP's architecture as well as a necessity for a finished master processor have predetermined Cyclone V family FPGA (Field Programmable Gate Array) (Altera) as the base of RSP implementation and Quartus II design software for its development. The powerful verification tools contained by Quartus II allow both reducing the time of obtaining the finished design and reducing the hardware expenses essentially. On the basis of the comparative analysis and selected criteria, the tools composition for debugging RSP is determined, and an optimal structure of hardware for debugging RSP is offered that allow for essential simplification of the verification process and for debugging RSP in a real hardware environment.

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